DMA interrupt enable bit/register

[gm_matthew]

I recently decided to try implementing proper IRQ deassertion on the PowerPC in Supermodel since it's been on the to-do list for quite some time, and in doing so I discovered a little quirk regarding DMA interrupts that so far no one else seems to have documented.

After making it so that the PowerPC no longer clears its own IRQ line and making the IRQ controller responsible for clearing interrupts, I came across the issue of some games hanging during boot. It turned out that these games were not acknowledging DMA interrupts so the IRQ controller would never clear the CPU IRQ line; this didn't matter when the PowerPC cleared its own IRQ line automatically but now it was causing the game to get stuck in an infinite loop of interrupts. Disabling DMA interrupts altogether wasn't an option as this caused other games to slow to a crawl (as they were dependent on each interrupt to trigger the next DMA request), so I became convinced that there had to be some way of controlling whether or not DMA interrupts are fired.

After testing all of the Step 2.x games to see which ones acknowledged DMA interrupts and which did not, as well as checking the Real3D DMA registers with each DMA copy, I noticed that games which acknowledged DMA interrupts set the dmaConfig register to 0x01 or 0x81, and those which did not set dmaConfig to 0x00 or 0x80. There was no reference to the purpose of the low bit of dmaConfig in either Supermodel or MAME's source code (MAME calls it m_dma_endian), so I deduced that it must be an undocumented IRQ enable bit. Sure enough when I set it so that DMA interrupts were only fired when this bit was set, all Step 2.x games worked. This leads me to conclude that the low bit of dmaConfig (register 0x0E) must indeed be an IRQ enable bit.

However, this only helped the Step 2.x games that use the proprietary DMA controller; Step 1.x games use the 53C810 SCSI controller instead, so I would need to find a similar solution. Fortunately I was able to find documentation on the 53C810 here that revealed the existence of a register called DIEN (DMA Interrupt Enable Register). After implementing this register in Supermodel and only firing interrupts when the appropriate bit is set, all Step 1.x games now work too.

I have already committed the changes to Supermodel (SVN 867), and I intend to submit these changes to MAME as well if I ever get round to compiling my own MAME build.

[Ian]

I saw your commit, really excellent work. I'm currently in a different country so can't test. Does this change the running of any of the games ?

[gm_matthew]

I saw your commit, really excellent work. I'm currently in a different country so can't test. Does this change the running of any of the games ?

I haven't noticed any dramatic differences. Sega Rally 2 should require slightly fewer (around 3 MHz) PowerPC cycles to run at full speed now; it does lots of small DMA transfers, each one of which used to generate a unnecessary interrupt and ended up wasting CPU cycles.