Bart,
I did a bit of poking around with frame timing (again). Looking this time only at the 2D rolling start bug. The rolling start bug exists as far as I can tell because we draw the frame at the wrong time The scroll values should apply to the next frame, instead they apply to the current one.
Anyway,
I put a bit of code in there to see where in the frame time the memory updates happen as a % of the frame time.
- Code: Select all
UINT64 fStart = 0;
UINT64 fEnd = 0;
void CModel3::RunMainBoardFrame(void) {
fStart = ppc_total_cycles();
fEnd = ppc_total_cycles() + frameCycles;
void CTileGen::WriteRAM32(unsigned addr, UINT32 data) {
double timeP = (double)(ppc_total_cycles() - fStart) / (fEnd - fStart) * 100;
printf("addr %x %lf\n", addr, timeP);
addr f88a8 0.111960
**truncated**
addr f84c4 0.620400
regs 60 80000000 0.624960
regs 64 80008000 0.625800
regs 68 80000000 0.626640
regs 6c 80000000 0.627480
regs 10 2 0.697920
regs c 3 0.702120
regs 10 4 2.651041
regs 10 8 2.654281 <- swap buffers should happen here before the scroll values are updated
addr f6580 5.467364
**truncated**
addr f65e0 5.478884
swap buffers
So the scroll values are written at 5.4% of the frame time .. Hmm that looks like the status change value.
Okay so I'll change the status change value and reboot the game
I changed the status change value to
statusCycles = (unsigned)((float)frameCycles * 10.5f/100.0f);
Now I get ..
addr f88a8 0.111960
**truncated**
addr f84c4 0.620400
regs 60 80000000 0.624960
regs 64 80008000 0.625800
regs 68 80000000 0.626640
regs 6c 80000000 0.627480
regs 10 2 0.697920
regs c 3 0.702120
regs 10 4 2.651041
regs 10 8 2.654281 <- swap buffers should happen here before the scroll values are updated
addr f6580 10.467364
**truncated**
addr f65e0 10.478884
swap buffers
Okay one last time, let's change it to
statusCycles = (unsigned)((float)frameCycles * 20.5f/100.0f);
Now the results are
addr f88a8 0.111960
**truncated**
addr f84c4 0.620400
regs 60 80000000 0.624960
regs 64 80008000 0.625800
regs 68 80000000 0.626640
regs 6c 80000000 0.627480
regs 10 2 0.697920
regs c 3 0.702120
regs 10 4 2.651041
regs 10 8 2.654281 <- swap buffers should happen here before the scroll values are updated
addr f6580 20.467364
**truncated**
addr f65e0 20.478884
swap buffers
The timing of the memory writes seem to be directly related to the status change bit, and if I was to guess it is probably simply the v-blank interval.
Mame uses this
- Code: Select all
READ64_MEMBER(model3_state::real3d_status_r)
{
m_real3d_status ^= 0xffffffffffffffffU;
if (offset == 0)
{
/* pretty sure this is VBLANK */
m_real3d_status &= ~0x0000000200000000U;
if (m_screen->vblank())
m_real3d_status |= 0x0000000200000000U;
return m_real3d_status;
}
return m_real3d_status;
}
I am pretty sure that must be correct ...